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dd240f6471
Add most recent SAM3X CMSIS files from Atmel. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
69 lines
5.9 KiB
C
69 lines
5.9 KiB
C
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM3XA_MATRIX_INSTANCE_
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#define _SAM3XA_MATRIX_INSTANCE_
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/* ========== Register definition for MATRIX peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_MATRIX_MCFG (0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */
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#define REG_MATRIX_SCFG (0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */
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#define REG_MATRIX_PRAS0 (0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
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#define REG_MATRIX_PRAS1 (0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
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#define REG_MATRIX_PRAS2 (0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
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#define REG_MATRIX_PRAS3 (0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
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#define REG_MATRIX_PRAS4 (0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
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#define REG_MATRIX_PRAS5 (0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
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#define REG_MATRIX_PRAS6 (0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
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#define REG_MATRIX_PRAS7 (0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
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#define REG_MATRIX_PRAS8 (0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
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#define REG_MATRIX_MRCR (0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */
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#define REG_CCFG_SYSIO (0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */
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#define REG_MATRIX_WPMR (0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */
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#define REG_MATRIX_WPSR (0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */
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#else
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#define REG_MATRIX_MCFG (*(__IO uint32_t*)0x400E0400U) /**< \brief (MATRIX) Master Configuration Register */
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#define REG_MATRIX_SCFG (*(__IO uint32_t*)0x400E0440U) /**< \brief (MATRIX) Slave Configuration Register */
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#define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x400E0480U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
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#define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x400E0488U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
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#define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x400E0490U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
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#define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x400E0498U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
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#define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400E04A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
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#define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400E04A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
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#define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400E04B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
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#define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400E04B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
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#define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400E04C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
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#define REG_MATRIX_MRCR (*(__IO uint32_t*)0x400E0500U) /**< \brief (MATRIX) Master Remap Control Register */
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#define REG_CCFG_SYSIO (*(__IO uint32_t*)0x400E0514U) /**< \brief (MATRIX) System I/O Configuration register */
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#define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400E05E4U) /**< \brief (MATRIX) Write Protect Mode Register */
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#define REG_MATRIX_WPSR (*(__I uint32_t*)0x400E05E8U) /**< \brief (MATRIX) Write Protect Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM3XA_MATRIX_INSTANCE_ */
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