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https://github.com/Klipper3d/klipper.git
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45cd3543e3
Commit ae89a659 caused a regression in the lpc176x UART handling.
After that commit the UART clock divisor would need to be 6.25 on
lpc1768 or 7.5 on lpc1769, but the code only supports whole numbers.
Set the PCLKSELx registers at startup and return to using full speed
peripheral clocks.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
36 lines
1.2 KiB
Diff
36 lines
1.2 KiB
Diff
--- device/system_LPC17xx.c 2018-05-02 12:23:57.292132454 -0400
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+++ device/system_LPC17xx.c 2021-05-04 10:08:17.637502030 -0400
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@@ -297,22 +297,19 @@
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#define CLKSRCSEL_Val 0x00000001
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#define PLL0_SETUP 1
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-#ifdef MCB1700
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-# define PLL0CFG_Val 0x00050063
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-# define PLL1_SETUP 1
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-# define PLL1CFG_Val 0x00000023
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-# define CCLKCFG_Val 0x00000003
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-# define USBCLKCFG_Val 0x00000000
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+#include "autoconf.h" // CONFIG_MACH_LPC1769
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+#if CONFIG_MACH_LPC1769
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+# define PLL0CFG_Val 0x0000000E
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#else
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-# define PLL0CFG_Val 0x0000000B
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-# define PLL1_SETUP 0
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-# define PLL1CFG_Val 0x00000000
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-# define CCLKCFG_Val 0x00000002
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-# define USBCLKCFG_Val 0x00000005
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+# define PLL0CFG_Val 0x00010018
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#endif
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+#define PLL1_SETUP 1
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+#define PLL1CFG_Val 0x00000023
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+#define CCLKCFG_Val 0x00000002
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+#define USBCLKCFG_Val 0x00000000
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-#define PCLKSEL0_Val 0x00000000
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-#define PCLKSEL1_Val 0x00000000
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+#define PCLKSEL0_Val 0x55515155
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+#define PCLKSEL1_Val 0x54555455
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#define PCONP_Val 0x042887DE
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#define CLKOUTCFG_Val 0x00000000
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