mirror of
https://github.com/Klipper3d/klipper.git
synced 2025-10-31 10:25:57 +01:00
e278552d44
This is in preparation for merging the sam3 and sam4 code. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
81 lines
6.4 KiB
C
81 lines
6.4 KiB
C
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM4E_SPI_INSTANCE_
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#define _SAM4E_SPI_INSTANCE_
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/* ========== Register definition for SPI peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_SPI_CR (0x40088000U) /**< \brief (SPI) Control Register */
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#define REG_SPI_MR (0x40088004U) /**< \brief (SPI) Mode Register */
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#define REG_SPI_RDR (0x40088008U) /**< \brief (SPI) Receive Data Register */
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#define REG_SPI_TDR (0x4008800CU) /**< \brief (SPI) Transmit Data Register */
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#define REG_SPI_SR (0x40088010U) /**< \brief (SPI) Status Register */
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#define REG_SPI_IER (0x40088014U) /**< \brief (SPI) Interrupt Enable Register */
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#define REG_SPI_IDR (0x40088018U) /**< \brief (SPI) Interrupt Disable Register */
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#define REG_SPI_IMR (0x4008801CU) /**< \brief (SPI) Interrupt Mask Register */
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#define REG_SPI_CSR (0x40088030U) /**< \brief (SPI) Chip Select Register */
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#define REG_SPI_WPMR (0x400880E4U) /**< \brief (SPI) Write Protection Control Register */
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#define REG_SPI_WPSR (0x400880E8U) /**< \brief (SPI) Write Protection Status Register */
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#define REG_SPI_RPR (0x40088100U) /**< \brief (SPI) Receive Pointer Register */
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#define REG_SPI_RCR (0x40088104U) /**< \brief (SPI) Receive Counter Register */
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#define REG_SPI_TPR (0x40088108U) /**< \brief (SPI) Transmit Pointer Register */
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#define REG_SPI_TCR (0x4008810CU) /**< \brief (SPI) Transmit Counter Register */
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#define REG_SPI_RNPR (0x40088110U) /**< \brief (SPI) Receive Next Pointer Register */
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#define REG_SPI_RNCR (0x40088114U) /**< \brief (SPI) Receive Next Counter Register */
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#define REG_SPI_TNPR (0x40088118U) /**< \brief (SPI) Transmit Next Pointer Register */
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#define REG_SPI_TNCR (0x4008811CU) /**< \brief (SPI) Transmit Next Counter Register */
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#define REG_SPI_PTCR (0x40088120U) /**< \brief (SPI) Transfer Control Register */
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#define REG_SPI_PTSR (0x40088124U) /**< \brief (SPI) Transfer Status Register */
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#else
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#define REG_SPI_CR (*(WoReg*)0x40088000U) /**< \brief (SPI) Control Register */
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#define REG_SPI_MR (*(RwReg*)0x40088004U) /**< \brief (SPI) Mode Register */
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#define REG_SPI_RDR (*(RoReg*)0x40088008U) /**< \brief (SPI) Receive Data Register */
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#define REG_SPI_TDR (*(WoReg*)0x4008800CU) /**< \brief (SPI) Transmit Data Register */
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#define REG_SPI_SR (*(RoReg*)0x40088010U) /**< \brief (SPI) Status Register */
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#define REG_SPI_IER (*(WoReg*)0x40088014U) /**< \brief (SPI) Interrupt Enable Register */
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#define REG_SPI_IDR (*(WoReg*)0x40088018U) /**< \brief (SPI) Interrupt Disable Register */
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#define REG_SPI_IMR (*(RoReg*)0x4008801CU) /**< \brief (SPI) Interrupt Mask Register */
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#define REG_SPI_CSR (*(RwReg*)0x40088030U) /**< \brief (SPI) Chip Select Register */
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#define REG_SPI_WPMR (*(RwReg*)0x400880E4U) /**< \brief (SPI) Write Protection Control Register */
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#define REG_SPI_WPSR (*(RoReg*)0x400880E8U) /**< \brief (SPI) Write Protection Status Register */
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#define REG_SPI_RPR (*(RwReg*)0x40088100U) /**< \brief (SPI) Receive Pointer Register */
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#define REG_SPI_RCR (*(RwReg*)0x40088104U) /**< \brief (SPI) Receive Counter Register */
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#define REG_SPI_TPR (*(RwReg*)0x40088108U) /**< \brief (SPI) Transmit Pointer Register */
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#define REG_SPI_TCR (*(RwReg*)0x4008810CU) /**< \brief (SPI) Transmit Counter Register */
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#define REG_SPI_RNPR (*(RwReg*)0x40088110U) /**< \brief (SPI) Receive Next Pointer Register */
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#define REG_SPI_RNCR (*(RwReg*)0x40088114U) /**< \brief (SPI) Receive Next Counter Register */
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#define REG_SPI_TNPR (*(RwReg*)0x40088118U) /**< \brief (SPI) Transmit Next Pointer Register */
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#define REG_SPI_TNCR (*(RwReg*)0x4008811CU) /**< \brief (SPI) Transmit Next Counter Register */
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#define REG_SPI_PTCR (*(WoReg*)0x40088120U) /**< \brief (SPI) Transfer Control Register */
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#define REG_SPI_PTSR (*(RoReg*)0x40088124U) /**< \brief (SPI) Transfer Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM4E_SPI_INSTANCE_ */
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