mirror of
https://github.com/Klipper3d/klipper.git
synced 2025-10-31 02:15:52 +01:00
e278552d44
This is in preparation for merging the sam3 and sam4 code. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
59 lines
4.5 KiB
C
59 lines
4.5 KiB
C
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM4E_CMCC_INSTANCE_
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#define _SAM4E_CMCC_INSTANCE_
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/* ========== Register definition for CMCC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_CMCC_TYPE (0x400C4000U) /**< \brief (CMCC) Cache Type Register */
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#define REG_CMCC_CFG (0x400C4004U) /**< \brief (CMCC) Cache Configuration Register */
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#define REG_CMCC_CTRL (0x400C4008U) /**< \brief (CMCC) Cache Control Register */
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#define REG_CMCC_SR (0x400C400CU) /**< \brief (CMCC) Cache Status Register */
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#define REG_CMCC_MAINT0 (0x400C4020U) /**< \brief (CMCC) Cache Maintenance Register 0 */
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#define REG_CMCC_MAINT1 (0x400C4024U) /**< \brief (CMCC) Cache Maintenance Register 1 */
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#define REG_CMCC_MCFG (0x400C4028U) /**< \brief (CMCC) Cache Monitor Configuration Register */
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#define REG_CMCC_MEN (0x400C402CU) /**< \brief (CMCC) Cache Monitor Enable Register */
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#define REG_CMCC_MCTRL (0x400C4030U) /**< \brief (CMCC) Cache Monitor Control Register */
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#define REG_CMCC_MSR (0x400C4034U) /**< \brief (CMCC) Cache Monitor Status Register */
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#else
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#define REG_CMCC_TYPE (*(RoReg*)0x400C4000U) /**< \brief (CMCC) Cache Type Register */
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#define REG_CMCC_CFG (*(RwReg*)0x400C4004U) /**< \brief (CMCC) Cache Configuration Register */
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#define REG_CMCC_CTRL (*(WoReg*)0x400C4008U) /**< \brief (CMCC) Cache Control Register */
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#define REG_CMCC_SR (*(RoReg*)0x400C400CU) /**< \brief (CMCC) Cache Status Register */
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#define REG_CMCC_MAINT0 (*(WoReg*)0x400C4020U) /**< \brief (CMCC) Cache Maintenance Register 0 */
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#define REG_CMCC_MAINT1 (*(WoReg*)0x400C4024U) /**< \brief (CMCC) Cache Maintenance Register 1 */
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#define REG_CMCC_MCFG (*(RwReg*)0x400C4028U) /**< \brief (CMCC) Cache Monitor Configuration Register */
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#define REG_CMCC_MEN (*(RwReg*)0x400C402CU) /**< \brief (CMCC) Cache Monitor Enable Register */
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#define REG_CMCC_MCTRL (*(WoReg*)0x400C4030U) /**< \brief (CMCC) Cache Monitor Control Register */
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#define REG_CMCC_MSR (*(RoReg*)0x400C4034U) /**< \brief (CMCC) Cache Monitor Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM4E_CMCC_INSTANCE_ */
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