mirror of
https://github.com/Klipper3d/klipper.git
synced 2025-10-31 18:36:09 +01:00
e278552d44
This is in preparation for merging the sam3 and sam4 code. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
85 lines
7.1 KiB
C
85 lines
7.1 KiB
C
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM4E_TWI0_INSTANCE_
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#define _SAM4E_TWI0_INSTANCE_
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/* ========== Register definition for TWI0 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_TWI0_CR (0x400A8000U) /**< \brief (TWI0) Control Register */
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#define REG_TWI0_MMR (0x400A8004U) /**< \brief (TWI0) Master Mode Register */
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#define REG_TWI0_SMR (0x400A8008U) /**< \brief (TWI0) Slave Mode Register */
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#define REG_TWI0_IADR (0x400A800CU) /**< \brief (TWI0) Internal Address Register */
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#define REG_TWI0_CWGR (0x400A8010U) /**< \brief (TWI0) Clock Waveform Generator Register */
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#define REG_TWI0_SR (0x400A8020U) /**< \brief (TWI0) Status Register */
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#define REG_TWI0_IER (0x400A8024U) /**< \brief (TWI0) Interrupt Enable Register */
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#define REG_TWI0_IDR (0x400A8028U) /**< \brief (TWI0) Interrupt Disable Register */
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#define REG_TWI0_IMR (0x400A802CU) /**< \brief (TWI0) Interrupt Mask Register */
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#define REG_TWI0_RHR (0x400A8030U) /**< \brief (TWI0) Receive Holding Register */
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#define REG_TWI0_THR (0x400A8034U) /**< \brief (TWI0) Transmit Holding Register */
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#define REG_TWI0_WPROT_MODE (0x400A80E4U) /**< \brief (TWI0) Protection Mode Register */
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#define REG_TWI0_WPROT_STATUS (0x400A80E8U) /**< \brief (TWI0) Protection Status Register */
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#define REG_TWI0_RPR (0x400A8100U) /**< \brief (TWI0) Receive Pointer Register */
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#define REG_TWI0_RCR (0x400A8104U) /**< \brief (TWI0) Receive Counter Register */
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#define REG_TWI0_TPR (0x400A8108U) /**< \brief (TWI0) Transmit Pointer Register */
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#define REG_TWI0_TCR (0x400A810CU) /**< \brief (TWI0) Transmit Counter Register */
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#define REG_TWI0_RNPR (0x400A8110U) /**< \brief (TWI0) Receive Next Pointer Register */
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#define REG_TWI0_RNCR (0x400A8114U) /**< \brief (TWI0) Receive Next Counter Register */
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#define REG_TWI0_TNPR (0x400A8118U) /**< \brief (TWI0) Transmit Next Pointer Register */
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#define REG_TWI0_TNCR (0x400A811CU) /**< \brief (TWI0) Transmit Next Counter Register */
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#define REG_TWI0_PTCR (0x400A8120U) /**< \brief (TWI0) Transfer Control Register */
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#define REG_TWI0_PTSR (0x400A8124U) /**< \brief (TWI0) Transfer Status Register */
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#else
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#define REG_TWI0_CR (*(WoReg*)0x400A8000U) /**< \brief (TWI0) Control Register */
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#define REG_TWI0_MMR (*(RwReg*)0x400A8004U) /**< \brief (TWI0) Master Mode Register */
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#define REG_TWI0_SMR (*(RwReg*)0x400A8008U) /**< \brief (TWI0) Slave Mode Register */
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#define REG_TWI0_IADR (*(RwReg*)0x400A800CU) /**< \brief (TWI0) Internal Address Register */
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#define REG_TWI0_CWGR (*(RwReg*)0x400A8010U) /**< \brief (TWI0) Clock Waveform Generator Register */
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#define REG_TWI0_SR (*(RoReg*)0x400A8020U) /**< \brief (TWI0) Status Register */
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#define REG_TWI0_IER (*(WoReg*)0x400A8024U) /**< \brief (TWI0) Interrupt Enable Register */
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#define REG_TWI0_IDR (*(WoReg*)0x400A8028U) /**< \brief (TWI0) Interrupt Disable Register */
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#define REG_TWI0_IMR (*(RoReg*)0x400A802CU) /**< \brief (TWI0) Interrupt Mask Register */
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#define REG_TWI0_RHR (*(RoReg*)0x400A8030U) /**< \brief (TWI0) Receive Holding Register */
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#define REG_TWI0_THR (*(WoReg*)0x400A8034U) /**< \brief (TWI0) Transmit Holding Register */
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#define REG_TWI0_WPROT_MODE (*(RwReg*)0x400A80E4U) /**< \brief (TWI0) Protection Mode Register */
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#define REG_TWI0_WPROT_STATUS (*(RoReg*)0x400A80E8U) /**< \brief (TWI0) Protection Status Register */
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#define REG_TWI0_RPR (*(RwReg*)0x400A8100U) /**< \brief (TWI0) Receive Pointer Register */
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#define REG_TWI0_RCR (*(RwReg*)0x400A8104U) /**< \brief (TWI0) Receive Counter Register */
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#define REG_TWI0_TPR (*(RwReg*)0x400A8108U) /**< \brief (TWI0) Transmit Pointer Register */
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#define REG_TWI0_TCR (*(RwReg*)0x400A810CU) /**< \brief (TWI0) Transmit Counter Register */
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#define REG_TWI0_RNPR (*(RwReg*)0x400A8110U) /**< \brief (TWI0) Receive Next Pointer Register */
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#define REG_TWI0_RNCR (*(RwReg*)0x400A8114U) /**< \brief (TWI0) Receive Next Counter Register */
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#define REG_TWI0_TNPR (*(RwReg*)0x400A8118U) /**< \brief (TWI0) Transmit Next Pointer Register */
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#define REG_TWI0_TNCR (*(RwReg*)0x400A811CU) /**< \brief (TWI0) Transmit Next Counter Register */
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#define REG_TWI0_PTCR (*(WoReg*)0x400A8120U) /**< \brief (TWI0) Transfer Control Register */
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#define REG_TWI0_PTSR (*(RoReg*)0x400A8124U) /**< \brief (TWI0) Transfer Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM4E_TWI0_INSTANCE_ */
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