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dd240f6471
Add most recent SAM3X CMSIS files from Atmel. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
61 lines
5.0 KiB
C
61 lines
5.0 KiB
C
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM3XA_SDRAMC_INSTANCE_
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#define _SAM3XA_SDRAMC_INSTANCE_
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/* ========== Register definition for SDRAMC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_SDRAMC_MR (0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */
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#define REG_SDRAMC_TR (0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
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#define REG_SDRAMC_CR (0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
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#define REG_SDRAMC_LPR (0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
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#define REG_SDRAMC_IER (0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
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#define REG_SDRAMC_IDR (0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
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#define REG_SDRAMC_IMR (0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
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#define REG_SDRAMC_ISR (0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
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#define REG_SDRAMC_MDR (0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
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#define REG_SDRAMC_CR1 (0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
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#define REG_SDRAMC_OCMS (0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */
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#else
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#define REG_SDRAMC_MR (*(__IO uint32_t*)0x400E0200U) /**< \brief (SDRAMC) SDRAMC Mode Register */
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#define REG_SDRAMC_TR (*(__IO uint32_t*)0x400E0204U) /**< \brief (SDRAMC) SDRAMC Refresh Timer Register */
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#define REG_SDRAMC_CR (*(__IO uint32_t*)0x400E0208U) /**< \brief (SDRAMC) SDRAMC Configuration Register */
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#define REG_SDRAMC_LPR (*(__IO uint32_t*)0x400E0210U) /**< \brief (SDRAMC) SDRAMC Low Power Register */
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#define REG_SDRAMC_IER (*(__O uint32_t*)0x400E0214U) /**< \brief (SDRAMC) SDRAMC Interrupt Enable Register */
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#define REG_SDRAMC_IDR (*(__O uint32_t*)0x400E0218U) /**< \brief (SDRAMC) SDRAMC Interrupt Disable Register */
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#define REG_SDRAMC_IMR (*(__I uint32_t*)0x400E021CU) /**< \brief (SDRAMC) SDRAMC Interrupt Mask Register */
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#define REG_SDRAMC_ISR (*(__I uint32_t*)0x400E0220U) /**< \brief (SDRAMC) SDRAMC Interrupt Status Register */
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#define REG_SDRAMC_MDR (*(__IO uint32_t*)0x400E0224U) /**< \brief (SDRAMC) SDRAMC Memory Device Register */
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#define REG_SDRAMC_CR1 (*(__IO uint32_t*)0x400E0228U) /**< \brief (SDRAMC) SDRAMC Configuration Register 1 */
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#define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x400E022CU) /**< \brief (SDRAMC) SDRAMC OCMS Register 1 */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM3XA_SDRAMC_INSTANCE_ */
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