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https://github.com/Klipper3d/klipper.git
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dd240f6471
Add most recent SAM3X CMSIS files from Atmel. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
91 lines
7.9 KiB
C
91 lines
7.9 KiB
C
/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM3XA_PMC_INSTANCE_
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#define _SAM3XA_PMC_INSTANCE_
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/* ========== Register definition for PMC peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_PMC_SCER (0x400E0600U) /**< \brief (PMC) System Clock Enable Register */
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#define REG_PMC_SCDR (0x400E0604U) /**< \brief (PMC) System Clock Disable Register */
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#define REG_PMC_SCSR (0x400E0608U) /**< \brief (PMC) System Clock Status Register */
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#define REG_PMC_PCER0 (0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
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#define REG_PMC_PCDR0 (0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
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#define REG_PMC_PCSR0 (0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
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#define REG_CKGR_UCKR (0x400E061CU) /**< \brief (PMC) UTMI Clock Register */
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#define REG_CKGR_MOR (0x400E0620U) /**< \brief (PMC) Main Oscillator Register */
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#define REG_CKGR_MCFR (0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */
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#define REG_CKGR_PLLAR (0x400E0628U) /**< \brief (PMC) PLLA Register */
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#define REG_PMC_MCKR (0x400E0630U) /**< \brief (PMC) Master Clock Register */
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#define REG_PMC_USB (0x400E0638U) /**< \brief (PMC) USB Clock Register */
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#define REG_PMC_PCK (0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */
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#define REG_PMC_IER (0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */
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#define REG_PMC_IDR (0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */
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#define REG_PMC_SR (0x400E0668U) /**< \brief (PMC) Status Register */
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#define REG_PMC_IMR (0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */
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#define REG_PMC_FSMR (0x400E0670U) /**< \brief (PMC) Fast Start-up Mode Register */
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#define REG_PMC_FSPR (0x400E0674U) /**< \brief (PMC) Fast Start-up Polarity Register */
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#define REG_PMC_FOCR (0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */
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#define REG_PMC_WPMR (0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */
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#define REG_PMC_WPSR (0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */
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#define REG_PMC_PCER1 (0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
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#define REG_PMC_PCDR1 (0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
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#define REG_PMC_PCSR1 (0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
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#define REG_PMC_PCR (0x400E070CU) /**< \brief (PMC) Peripheral Control Register */
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#else
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#define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< \brief (PMC) System Clock Enable Register */
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#define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< \brief (PMC) System Clock Disable Register */
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#define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< \brief (PMC) System Clock Status Register */
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#define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
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#define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
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#define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
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#define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< \brief (PMC) UTMI Clock Register */
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#define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< \brief (PMC) Main Oscillator Register */
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#define REG_CKGR_MCFR (*(__I uint32_t*)0x400E0624U) /**< \brief (PMC) Main Clock Frequency Register */
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#define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< \brief (PMC) PLLA Register */
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#define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< \brief (PMC) Master Clock Register */
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#define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< \brief (PMC) USB Clock Register */
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#define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< \brief (PMC) Programmable Clock 0 Register */
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#define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< \brief (PMC) Interrupt Enable Register */
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#define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< \brief (PMC) Interrupt Disable Register */
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#define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< \brief (PMC) Status Register */
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#define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< \brief (PMC) Interrupt Mask Register */
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#define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< \brief (PMC) Fast Start-up Mode Register */
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#define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< \brief (PMC) Fast Start-up Polarity Register */
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#define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< \brief (PMC) Fault Output Clear Register */
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#define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< \brief (PMC) Write Protect Mode Register */
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#define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< \brief (PMC) Write Protect Status Register */
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#define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
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#define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
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#define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
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#define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< \brief (PMC) Peripheral Control Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM3XA_PMC_INSTANCE_ */
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