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75d5737211
Add a fully functional STM32F1 port, currently mostly targeting STM32F103 microcontrollers. This requires an 8 MHz XTAL. The maximum possible step rate is around 282K steps per second. This uses stm32flash to burn the firmware. The bootloader needs to be started by setting BOOT0 to 1 and resetting the MCU. There is no automatic bootloader, unlike on Arduino. Signed-off-by: Grigori Goronzy <greg@kinoho.net>
1342 lines
53 KiB
C
1342 lines
53 KiB
C
/**
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******************************************************************************
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* @file stm32f1xx_hal_adc_ex.c
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* @author MCD Application Team
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* @version V1.1.1
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* @date 12-May-2017
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* @brief This file provides firmware functions to manage the following
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* functionalities of the Analog to Digital Convertor (ADC)
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* peripheral:
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* + Operation functions
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* ++ Start, stop, get result of conversions of injected
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* group, using 2 possible modes: polling, interruption.
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* ++ Multimode feature (available on devices with 2 ADCs or more)
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* ++ Calibration (ADC automatic self-calibration)
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* + Control functions
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* ++ Channels configuration on injected group
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* Other functions (generic functions) are available in file
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* "stm32f1xx_hal_adc.c".
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*
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@verbatim
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[..]
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(@) Sections "ADC peripheral features" and "How to use this driver" are
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available in file of generic functions "stm32f1xx_hal_adc.c".
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[..]
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_hal.h"
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/** @addtogroup STM32F1xx_HAL_Driver
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* @{
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*/
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/** @defgroup ADCEx ADCEx
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* @brief ADC Extension HAL module driver
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* @{
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*/
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#ifdef HAL_ADC_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup ADCEx_Private_Constants ADCEx Private Constants
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* @{
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*/
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/* Delay for ADC calibration: */
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/* Hardware prerequisite before starting a calibration: the ADC must have */
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/* been in power-on state for at least two ADC clock cycles. */
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/* Unit: ADC clock cycles */
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#define ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES 2U
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/* Timeout value for ADC calibration */
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/* Value defined to be higher than worst cases: low clocks freq, */
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/* maximum prescaler. */
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/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */
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/* prescaler 4, sampling time 12.5 ADC clock cycles, resolution 12 bits. */
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/* Unit: ms */
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#define ADC_CALIBRATION_TIMEOUT 10U
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/* Delay for temperature sensor stabilization time. */
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/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
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/* Unit: us */
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#define ADC_TEMPSENSOR_DELAY_US 10U
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Private functions ---------------------------------------------------------*/
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/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
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* @{
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*/
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/** @defgroup ADCEx_Exported_Functions_Group1 Extended Extended IO operation functions
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* @brief Extended Extended Input and Output operation functions
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*
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@verbatim
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===============================================================================
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##### IO operation functions #####
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===============================================================================
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[..] This section provides functions allowing to:
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(+) Start conversion of injected group.
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(+) Stop conversion of injected group.
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(+) Poll for conversion complete on injected group.
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(+) Get result of injected channel conversion.
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(+) Start conversion of injected group and enable interruptions.
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(+) Stop conversion of injected group and disable interruptions.
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(+) Start multimode and enable DMA transfer.
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(+) Stop multimode and disable ADC DMA transfer.
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(+) Get result of multimode conversion.
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(+) Perform the ADC self-calibration for single or differential ending.
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(+) Get calibration factors for single or differential ending.
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(+) Set calibration factors for single or differential ending.
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@endverbatim
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* @{
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*/
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/**
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* @brief Perform an ADC automatic self-calibration
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* Calibration prerequisite: ADC must be disabled (execute this
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* function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
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* During calibration process, ADC is enabled. ADC is let enabled at
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* the completion of this function.
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* @param hadc: ADC handle
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
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{
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HAL_StatusTypeDef tmp_hal_status = HAL_OK;
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uint32_t tickstart;
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__IO uint32_t wait_loop_index = 0U;
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/* Check the parameters */
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assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
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/* Process locked */
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__HAL_LOCK(hadc);
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/* 1. Calibration prerequisite: */
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/* - ADC must be disabled for at least two ADC clock cycles in disable */
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/* mode before ADC enable */
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/* Stop potential conversion on going, on regular and injected groups */
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/* Disable ADC peripheral */
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tmp_hal_status = ADC_ConversionStop_Disable(hadc);
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/* Check if ADC is effectively disabled */
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if (tmp_hal_status == HAL_OK)
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{
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/* Set ADC state */
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ADC_STATE_CLR_SET(hadc->State,
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HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
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HAL_ADC_STATE_BUSY_INTERNAL);
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/* Hardware prerequisite: delay before starting the calibration. */
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/* - Computation of CPU clock cycles corresponding to ADC clock cycles. */
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/* - Wait for the expected ADC clock cycles delay */
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wait_loop_index = ((SystemCoreClock
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/ HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
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* ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES );
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while(wait_loop_index != 0U)
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{
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wait_loop_index--;
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}
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/* 2. Enable the ADC peripheral */
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ADC_Enable(hadc);
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/* 3. Resets ADC calibration registers */
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SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL);
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tickstart = HAL_GetTick();
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/* Wait for calibration reset completion */
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while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL))
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{
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if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
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{
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/* Update ADC state machine to error */
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ADC_STATE_CLR_SET(hadc->State,
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HAL_ADC_STATE_BUSY_INTERNAL,
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HAL_ADC_STATE_ERROR_INTERNAL);
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/* Process unlocked */
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__HAL_UNLOCK(hadc);
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return HAL_ERROR;
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}
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}
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/* 4. Start ADC calibration */
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SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL);
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tickstart = HAL_GetTick();
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/* Wait for calibration completion */
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while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL))
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{
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if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT)
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{
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/* Update ADC state machine to error */
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ADC_STATE_CLR_SET(hadc->State,
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HAL_ADC_STATE_BUSY_INTERNAL,
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HAL_ADC_STATE_ERROR_INTERNAL);
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/* Process unlocked */
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__HAL_UNLOCK(hadc);
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return HAL_ERROR;
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}
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}
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/* Set ADC state */
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ADC_STATE_CLR_SET(hadc->State,
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HAL_ADC_STATE_BUSY_INTERNAL,
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HAL_ADC_STATE_READY);
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}
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/* Process unlocked */
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__HAL_UNLOCK(hadc);
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/* Return function status */
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return tmp_hal_status;
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}
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/**
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* @brief Enables ADC, starts conversion of injected group.
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* Interruptions enabled in this function: None.
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* @param hadc: ADC handle
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
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{
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HAL_StatusTypeDef tmp_hal_status = HAL_OK;
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/* Check the parameters */
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assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
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/* Process locked */
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__HAL_LOCK(hadc);
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/* Enable the ADC peripheral */
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tmp_hal_status = ADC_Enable(hadc);
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/* Start conversion if ADC is effectively enabled */
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if (tmp_hal_status == HAL_OK)
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{
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/* Set ADC state */
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/* - Clear state bitfield related to injected group conversion results */
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/* - Set state bitfield related to injected operation */
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ADC_STATE_CLR_SET(hadc->State,
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HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
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HAL_ADC_STATE_INJ_BUSY);
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/* Case of independent mode or multimode (for devices with several ADCs): */
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/* Set multimode state. */
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if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
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{
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CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
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}
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else
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{
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SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
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}
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/* Check if a regular conversion is ongoing */
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/* Note: On this device, there is no ADC error code fields related to */
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/* conversions on group injected only. In case of conversion on */
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/* going on group regular, no error code is reset. */
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if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
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{
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/* Reset ADC all error code fields */
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ADC_CLEAR_ERRORCODE(hadc);
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}
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/* Process unlocked */
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/* Unlock before starting ADC conversions: in case of potential */
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/* interruption, to let the process to ADC IRQ Handler. */
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__HAL_UNLOCK(hadc);
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/* Clear injected group conversion flag */
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/* (To ensure of no unknown state from potential previous ADC operations) */
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__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
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/* Enable conversion of injected group. */
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/* If software start has been selected, conversion starts immediately. */
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/* If external trigger has been selected, conversion will start at next */
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/* trigger event. */
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/* If automatic injected conversion is enabled, conversion will start */
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/* after next regular group conversion. */
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/* Case of multimode enabled (for devices with several ADCs): if ADC is */
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/* slave, ADC is enabled only (conversion is not started). If ADC is */
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/* master, ADC is enabled and conversion is started. */
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if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
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{
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if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
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ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
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{
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/* Start ADC conversion on injected group with SW start */
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SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
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}
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else
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{
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/* Start ADC conversion on injected group with external trigger */
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SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
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}
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}
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}
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else
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{
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/* Process unlocked */
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__HAL_UNLOCK(hadc);
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}
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/* Return function status */
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return tmp_hal_status;
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}
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/**
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* @brief Stop conversion of injected channels. Disable ADC peripheral if
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* no regular conversion is on going.
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* @note If ADC must be disabled and if conversion is on going on
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* regular group, function HAL_ADC_Stop must be used to stop both
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* injected and regular groups, and disable the ADC.
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* @note If injected group mode auto-injection is enabled,
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* function HAL_ADC_Stop must be used.
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* @note In case of auto-injection mode, HAL_ADC_Stop must be used.
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* @param hadc: ADC handle
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* @retval None
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*/
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HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
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{
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HAL_StatusTypeDef tmp_hal_status = HAL_OK;
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/* Check the parameters */
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assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
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/* Process locked */
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__HAL_LOCK(hadc);
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/* Stop potential conversion and disable ADC peripheral */
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/* Conditioned to: */
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/* - No conversion on the other group (regular group) is intended to */
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/* continue (injected and regular groups stop conversion and ADC disable */
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/* are common) */
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/* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
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if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
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HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
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{
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/* Stop potential conversion on going, on regular and injected groups */
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/* Disable ADC peripheral */
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tmp_hal_status = ADC_ConversionStop_Disable(hadc);
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/* Check if ADC is effectively disabled */
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if (tmp_hal_status == HAL_OK)
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{
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/* Set ADC state */
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ADC_STATE_CLR_SET(hadc->State,
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HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
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HAL_ADC_STATE_READY);
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}
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}
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else
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{
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/* Update ADC state machine to error */
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SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
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tmp_hal_status = HAL_ERROR;
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}
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/* Process unlocked */
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__HAL_UNLOCK(hadc);
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/* Return function status */
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return tmp_hal_status;
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}
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/**
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* @brief Wait for injected group conversion to be completed.
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* @param hadc: ADC handle
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* @param Timeout: Timeout value in millisecond.
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
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{
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uint32_t tickstart;
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/* Variables for polling in case of scan mode enabled and polling for each */
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/* conversion. */
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__IO uint32_t Conversion_Timeout_CPU_cycles = 0U;
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uint32_t Conversion_Timeout_CPU_cycles_max = 0U;
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/* Check the parameters */
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assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
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/* Get timeout */
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tickstart = HAL_GetTick();
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/* Polling for end of conversion: differentiation if single/sequence */
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/* conversion. */
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/* For injected group, flag JEOC is set only at the end of the sequence, */
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/* not for each conversion within the sequence. */
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/* - If single conversion for injected group (scan mode disabled or */
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/* InjectedNbrOfConversion ==1), flag JEOC is used to determine the */
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/* conversion completion. */
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/* - If sequence conversion for injected group (scan mode enabled and */
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/* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
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/* sequence. */
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/* To poll for each conversion, the maximum conversion time is computed */
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/* from ADC conversion time (selected sampling time + conversion time of */
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/* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */
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/* settings, conversion time range can be from 28 to 32256 CPU cycles). */
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/* As flag JEOC is not set after each conversion, no timeout status can */
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/* be set. */
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if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET)
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{
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/* Wait until End of Conversion flag is raised */
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while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
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{
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/* Check if timeout is disabled (set to infinite wait) */
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if(Timeout != HAL_MAX_DELAY)
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{
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if((Timeout == 0U) || ((HAL_GetTick() - tickstart ) > Timeout))
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{
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/* Update ADC state machine to timeout */
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SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
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/* Process unlocked */
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__HAL_UNLOCK(hadc);
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return HAL_TIMEOUT;
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}
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}
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}
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}
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else
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{
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/* Replace polling by wait for maximum conversion time */
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/* - Computation of CPU clock cycles corresponding to ADC clock cycles */
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/* and ADC maximum conversion cycles on all channels. */
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/* - Wait for the expected ADC clock cycles delay */
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Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock
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/ HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC))
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* ADC_CONVCYCLES_MAX_RANGE(hadc) );
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while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max)
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{
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/* Check if timeout is disabled (set to infinite wait) */
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if(Timeout != HAL_MAX_DELAY)
|
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{
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if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
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{
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/* Update ADC state machine to timeout */
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SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
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/* Process unlocked */
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__HAL_UNLOCK(hadc);
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return HAL_TIMEOUT;
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}
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}
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Conversion_Timeout_CPU_cycles ++;
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}
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}
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/* Clear injected group conversion flag */
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/* Note: On STM32F1 ADC, clear regular conversion flag raised */
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/* simultaneously. */
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__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC);
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/* Update ADC state machine */
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SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
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|
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/* Determine whether any further conversion upcoming on group injected */
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/* by external trigger or by automatic injected conversion */
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/* from group regular. */
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if(ADC_IS_SOFTWARE_START_INJECTED(hadc) ||
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(HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&
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(ADC_IS_SOFTWARE_START_REGULAR(hadc) &&
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(hadc->Init.ContinuousConvMode == DISABLE) ) ) )
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{
|
|
/* Set ADC state */
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
|
|
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
|
|
}
|
|
}
|
|
|
|
/* Return ADC state */
|
|
return HAL_OK;
|
|
}
|
|
|
|
/**
|
|
* @brief Enables ADC, starts conversion of injected group with interruption.
|
|
* - JEOC (end of conversion of injected group)
|
|
* Each of these interruptions has its dedicated callback function.
|
|
* @param hadc: ADC handle
|
|
* @retval HAL status.
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
/* Enable the ADC peripheral */
|
|
tmp_hal_status = ADC_Enable(hadc);
|
|
|
|
/* Start conversion if ADC is effectively enabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Set ADC state */
|
|
/* - Clear state bitfield related to injected group conversion results */
|
|
/* - Set state bitfield related to injected operation */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
|
|
HAL_ADC_STATE_INJ_BUSY);
|
|
|
|
/* Case of independent mode or multimode (for devices with several ADCs): */
|
|
/* Set multimode state. */
|
|
if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc))
|
|
{
|
|
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
|
}
|
|
else
|
|
{
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
|
|
}
|
|
|
|
/* Check if a regular conversion is ongoing */
|
|
/* Note: On this device, there is no ADC error code fields related to */
|
|
/* conversions on group injected only. In case of conversion on */
|
|
/* going on group regular, no error code is reset. */
|
|
if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY))
|
|
{
|
|
/* Reset ADC all error code fields */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
}
|
|
|
|
/* Process unlocked */
|
|
/* Unlock before starting ADC conversions: in case of potential */
|
|
/* interruption, to let the process to ADC IRQ Handler. */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Clear injected group conversion flag */
|
|
/* (To ensure of no unknown state from potential previous ADC operations) */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
|
|
|
|
/* Enable end of conversion interrupt for injected channels */
|
|
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
|
|
|
|
/* Start conversion of injected group if software start has been selected */
|
|
/* and if automatic injected conversion is disabled. */
|
|
/* If external trigger has been selected, conversion will start at next */
|
|
/* trigger event. */
|
|
/* If automatic injected conversion is enabled, conversion will start */
|
|
/* after next regular group conversion. */
|
|
if (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO))
|
|
{
|
|
if (ADC_IS_SOFTWARE_START_INJECTED(hadc) &&
|
|
ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc) )
|
|
{
|
|
/* Start ADC conversion on injected group with SW start */
|
|
SET_BIT(hadc->Instance->CR2, (ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG));
|
|
}
|
|
else
|
|
{
|
|
/* Start ADC conversion on injected group with external trigger */
|
|
SET_BIT(hadc->Instance->CR2, ADC_CR2_JEXTTRIG);
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @brief Stop conversion of injected channels, disable interruption of
|
|
* end-of-conversion. Disable ADC peripheral if no regular conversion
|
|
* is on going.
|
|
* @note If ADC must be disabled and if conversion is on going on
|
|
* regular group, function HAL_ADC_Stop must be used to stop both
|
|
* injected and regular groups, and disable the ADC.
|
|
* @note If injected group mode auto-injection is enabled,
|
|
* function HAL_ADC_Stop must be used.
|
|
* @param hadc: ADC handle
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
/* Stop potential conversion and disable ADC peripheral */
|
|
/* Conditioned to: */
|
|
/* - No conversion on the other group (regular group) is intended to */
|
|
/* continue (injected and regular groups stop conversion and ADC disable */
|
|
/* are common) */
|
|
/* - In case of auto-injection mode, HAL_ADC_Stop must be used. */
|
|
if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) &&
|
|
HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) )
|
|
{
|
|
/* Stop potential conversion on going, on regular and injected groups */
|
|
/* Disable ADC peripheral */
|
|
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
|
|
|
|
/* Check if ADC is effectively disabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Disable ADC end of conversion interrupt for injected channels */
|
|
__HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
|
|
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
|
/**
|
|
* @brief Enables ADC, starts conversion of regular group and transfers result
|
|
* through DMA.
|
|
* Multimode must have been previously configured using
|
|
* HAL_ADCEx_MultiModeConfigChannel() function.
|
|
* Interruptions enabled in this function:
|
|
* - DMA transfer complete
|
|
* - DMA half transfer
|
|
* Each of these interruptions has its dedicated callback function.
|
|
* @note: On STM32F1 devices, ADC slave regular group must be configured
|
|
* with conversion trigger ADC_SOFTWARE_START.
|
|
* @note: ADC slave can be enabled preliminarily using single-mode
|
|
* HAL_ADC_Start() function.
|
|
* @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
|
|
* @param pData: The destination Buffer address.
|
|
* @param Length: The length of data to be transferred from ADC peripheral to memory.
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
ADC_HandleTypeDef tmphadcSlave;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
|
|
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
/* Set a temporary handle of the ADC slave associated to the ADC master */
|
|
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
|
|
|
|
/* On STM32F1 devices, ADC slave regular group must be configured with */
|
|
/* conversion trigger ADC_SOFTWARE_START. */
|
|
/* Note: External trigger of ADC slave must be enabled, it is already done */
|
|
/* into function "HAL_ADC_Init()". */
|
|
if(!ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave))
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Enable the ADC peripherals: master and slave (in case if not already */
|
|
/* enabled previously) */
|
|
tmp_hal_status = ADC_Enable(hadc);
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
tmp_hal_status = ADC_Enable(&tmphadcSlave);
|
|
}
|
|
|
|
/* Start conversion if all ADCs of multimode are effectively enabled */
|
|
if (tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Set ADC state (ADC master) */
|
|
/* - Clear state bitfield related to regular group conversion results */
|
|
/* - Set state bitfield related to regular operation */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_MULTIMODE_SLAVE,
|
|
HAL_ADC_STATE_REG_BUSY);
|
|
|
|
/* If conversions on group regular are also triggering group injected, */
|
|
/* update ADC state. */
|
|
if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET)
|
|
{
|
|
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
|
|
}
|
|
|
|
/* Process unlocked */
|
|
/* Unlock before starting ADC conversions: in case of potential */
|
|
/* interruption, to let the process to ADC IRQ Handler. */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Set ADC error code to none */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
|
|
|
|
/* Set the DMA transfer complete callback */
|
|
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
|
|
|
|
/* Set the DMA half transfer complete callback */
|
|
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
|
|
|
|
/* Set the DMA error callback */
|
|
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
|
|
|
|
|
|
/* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */
|
|
/* start (in case of SW start): */
|
|
|
|
/* Clear regular group conversion flag and overrun flag */
|
|
/* (To ensure of no unknown state from potential previous ADC operations) */
|
|
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
|
|
|
|
/* Enable ADC DMA mode of ADC master */
|
|
SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
|
|
|
|
/* Start the DMA channel */
|
|
HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
|
|
|
|
/* Start conversion of regular group if software start has been selected. */
|
|
/* If external trigger has been selected, conversion will start at next */
|
|
/* trigger event. */
|
|
/* Note: Alternate trigger for single conversion could be to force an */
|
|
/* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
|
|
if (ADC_IS_SOFTWARE_START_REGULAR(hadc))
|
|
{
|
|
/* Start ADC conversion on regular group with SW start */
|
|
SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG));
|
|
}
|
|
else
|
|
{
|
|
/* Start ADC conversion on regular group with external trigger */
|
|
SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
|
|
/**
|
|
* @brief Stop ADC conversion of regular group (and injected channels in
|
|
* case of auto_injection mode), disable ADC DMA transfer, disable
|
|
* ADC peripheral.
|
|
* @note Multimode is kept enabled after this function. To disable multimode
|
|
* (set with HAL_ADCEx_MultiModeConfigChannel(), ADC must be
|
|
* reinitialized using HAL_ADC_Init() or HAL_ADC_ReInit().
|
|
* @note In case of DMA configured in circular mode, function
|
|
* HAL_ADC_Stop_DMA must be called after this function with handle of
|
|
* ADC slave, to properly disable the DMA channel.
|
|
* @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
ADC_HandleTypeDef tmphadcSlave;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
|
|
|
|
/* Stop potential conversion on going, on regular and injected groups */
|
|
/* Disable ADC master peripheral */
|
|
tmp_hal_status = ADC_ConversionStop_Disable(hadc);
|
|
|
|
/* Check if ADC is effectively disabled */
|
|
if(tmp_hal_status == HAL_OK)
|
|
{
|
|
/* Set a temporary handle of the ADC slave associated to the ADC master */
|
|
ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
|
|
|
|
/* Disable ADC slave peripheral */
|
|
tmp_hal_status = ADC_ConversionStop_Disable(&tmphadcSlave);
|
|
|
|
/* Check if ADC is effectively disabled */
|
|
if(tmp_hal_status != HAL_OK)
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
return HAL_ERROR;
|
|
}
|
|
|
|
/* Disable ADC DMA mode */
|
|
CLEAR_BIT(hadc->Instance->CR2, ADC_CR2_DMA);
|
|
|
|
/* Reset configuration of ADC DMA continuous request for dual mode */
|
|
CLEAR_BIT(hadc->Instance->CR1, ADC_CR1_DUALMOD);
|
|
|
|
/* Disable the DMA channel (in case of DMA in circular mode or stop while */
|
|
/* while DMA transfer is on going) */
|
|
tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
|
|
|
|
/* Change ADC state (ADC master) */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
|
|
HAL_ADC_STATE_READY);
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
|
|
|
/**
|
|
* @brief Get ADC injected group conversion result.
|
|
* @note Reading register JDRx automatically clears ADC flag JEOC
|
|
* (ADC group injected end of unitary conversion).
|
|
* @note This function does not clear ADC flag JEOS
|
|
* (ADC group injected end of sequence conversion)
|
|
* Occurrence of flag JEOS rising:
|
|
* - If sequencer is composed of 1 rank, flag JEOS is equivalent
|
|
* to flag JEOC.
|
|
* - If sequencer is composed of several ranks, during the scan
|
|
* sequence flag JEOC only is raised, at the end of the scan sequence
|
|
* both flags JEOC and EOS are raised.
|
|
* Flag JEOS must not be cleared by this function because
|
|
* it would not be compliant with low power features
|
|
* (feature low power auto-wait, not available on all STM32 families).
|
|
* To clear this flag, either use function:
|
|
* in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
|
|
* model polling: @ref HAL_ADCEx_InjectedPollForConversion()
|
|
* or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
|
|
* @param hadc: ADC handle
|
|
* @param InjectedRank: the converted ADC injected rank.
|
|
* This parameter can be one of the following values:
|
|
* @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
|
|
* @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
|
|
* @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
|
|
* @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
|
|
* @retval ADC group injected conversion data
|
|
*/
|
|
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
|
|
{
|
|
uint32_t tmp_jdr = 0U;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
|
|
|
|
/* Get ADC converted value */
|
|
switch(InjectedRank)
|
|
{
|
|
case ADC_INJECTED_RANK_4:
|
|
tmp_jdr = hadc->Instance->JDR4;
|
|
break;
|
|
case ADC_INJECTED_RANK_3:
|
|
tmp_jdr = hadc->Instance->JDR3;
|
|
break;
|
|
case ADC_INJECTED_RANK_2:
|
|
tmp_jdr = hadc->Instance->JDR2;
|
|
break;
|
|
case ADC_INJECTED_RANK_1:
|
|
default:
|
|
tmp_jdr = hadc->Instance->JDR1;
|
|
break;
|
|
}
|
|
|
|
/* Return ADC converted value */
|
|
return tmp_jdr;
|
|
}
|
|
|
|
#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
|
|
/**
|
|
* @brief Returns the last ADC Master&Slave regular conversions results data
|
|
* in the selected multi mode.
|
|
* @param hadc: ADC handle of ADC master (handle of ADC slave must not be used)
|
|
* @retval The converted data value.
|
|
*/
|
|
uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
|
|
{
|
|
uint32_t tmpDR = 0U;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
|
|
|
|
/* Note: EOC flag is not cleared here by software because automatically */
|
|
/* cleared by hardware when reading register DR. */
|
|
|
|
/* On STM32F1 devices, ADC1 data register DR contains ADC2 conversions */
|
|
/* only if ADC1 DMA mode is enabled. */
|
|
tmpDR = hadc->Instance->DR;
|
|
|
|
if (HAL_IS_BIT_CLR(ADC1->CR2, ADC_CR2_DMA))
|
|
{
|
|
tmpDR |= (ADC2->DR << 16U);
|
|
}
|
|
|
|
/* Return ADC converted value */
|
|
return tmpDR;
|
|
}
|
|
#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
|
|
|
|
/**
|
|
* @brief Injected conversion complete callback in non blocking mode
|
|
* @param hadc: ADC handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
|
|
{
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(hadc);
|
|
/* NOTE : This function Should not be modified, when the callback is needed,
|
|
the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
|
|
*/
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
|
|
* @brief Extended Peripheral Control functions
|
|
*
|
|
@verbatim
|
|
===============================================================================
|
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##### Peripheral Control functions #####
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===============================================================================
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[..] This section provides functions allowing to:
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(+) Configure channels on injected group
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(+) Configure multimode
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@endverbatim
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* @{
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*/
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/**
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* @brief Configures the ADC injected group and the selected channel to be
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* linked to the injected group.
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* @note Possibility to update parameters on the fly:
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* This function initializes injected group, following calls to this
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* function can be used to reconfigure some parameters of structure
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* "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
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* The setting of these parameters is conditioned to ADC state:
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* this function must be called when ADC is not under conversion.
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* @param hadc: ADC handle
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* @param sConfigInjected: Structure of ADC injected group and ADC channel for
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* injected group.
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* @retval None
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*/
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HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
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{
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HAL_StatusTypeDef tmp_hal_status = HAL_OK;
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__IO uint32_t wait_loop_index = 0U;
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/* Check the parameters */
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assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
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assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
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assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
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assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
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assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
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assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
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if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
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{
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assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
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assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
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assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
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}
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/* Process locked */
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__HAL_LOCK(hadc);
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/* Configuration of injected group sequencer: */
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/* - if scan mode is disabled, injected channels sequence length is set to */
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/* 0x00: 1 channel converted (channel on regular rank 1) */
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/* Parameter "InjectedNbrOfConversion" is discarded. */
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/* Note: Scan mode is present by hardware on this device and, if */
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/* disabled, discards automatically nb of conversions. Anyway, nb of */
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/* conversions is forced to 0x00 for alignment over all STM32 devices. */
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/* - if scan mode is enabled, injected channels sequence length is set to */
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/* parameter "InjectedNbrOfConversion". */
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if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
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{
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if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
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{
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/* Clear the old SQx bits for all injected ranks */
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MODIFY_REG(hadc->Instance->JSQR ,
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ADC_JSQR_JL |
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ADC_JSQR_JSQ4 |
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ADC_JSQR_JSQ3 |
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ADC_JSQR_JSQ2 |
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ADC_JSQR_JSQ1 ,
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ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
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ADC_INJECTED_RANK_1,
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0x01U));
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}
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/* If another injected rank than rank1 was intended to be set, and could */
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/* not due to ScanConvMode disabled, error is reported. */
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else
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{
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/* Update ADC state machine to error */
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SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
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tmp_hal_status = HAL_ERROR;
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}
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}
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else
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{
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/* Since injected channels rank conv. order depends on total number of */
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/* injected conversions, selected rank must be below or equal to total */
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/* number of injected conversions to be updated. */
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if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
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{
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/* Clear the old SQx bits for the selected rank */
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/* Set the SQx bits for the selected rank */
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MODIFY_REG(hadc->Instance->JSQR ,
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ADC_JSQR_JL |
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ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
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sConfigInjected->InjectedRank,
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sConfigInjected->InjectedNbrOfConversion) ,
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ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) |
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ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel,
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sConfigInjected->InjectedRank,
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sConfigInjected->InjectedNbrOfConversion) );
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}
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else
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{
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/* Clear the old SQx bits for the selected rank */
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MODIFY_REG(hadc->Instance->JSQR ,
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ADC_JSQR_JL |
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ADC_JSQR_RK_JL(ADC_JSQR_JSQ1,
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sConfigInjected->InjectedRank,
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sConfigInjected->InjectedNbrOfConversion) ,
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0x00000000U);
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}
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}
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/* Configuration of injected group */
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/* Parameters update conditioned to ADC state: */
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/* Parameters that can be updated only when ADC is disabled: */
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/* - external trigger to start conversion */
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/* Parameters update not conditioned to ADC state: */
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/* - Automatic injected conversion */
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/* - Injected discontinuous mode */
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/* Note: In case of ADC already enabled, caution to not launch an unwanted */
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/* conversion while modifying register CR2 by writing 1 to bit ADON. */
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if (ADC_IS_ENABLE(hadc) == RESET)
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{
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MODIFY_REG(hadc->Instance->CR2 ,
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ADC_CR2_JEXTSEL |
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ADC_CR2_ADON ,
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ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) );
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}
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/* Configuration of injected group */
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/* - Automatic injected conversion */
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/* - Injected discontinuous mode */
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/* Automatic injected conversion can be enabled if injected group */
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/* external triggers are disabled. */
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if (sConfigInjected->AutoInjectedConv == ENABLE)
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{
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if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
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{
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SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
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}
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else
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{
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/* Update ADC state machine to error */
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SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
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tmp_hal_status = HAL_ERROR;
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}
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}
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/* Injected discontinuous can be enabled only if auto-injected mode is */
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/* disabled. */
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if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
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{
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if (sConfigInjected->AutoInjectedConv == DISABLE)
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{
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SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
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}
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else
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{
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/* Update ADC state machine to error */
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SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
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tmp_hal_status = HAL_ERROR;
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}
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}
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/* InjectedChannel sampling time configuration */
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/* For channels 10 to 17 */
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if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10)
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{
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MODIFY_REG(hadc->Instance->SMPR1 ,
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ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel) ,
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ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
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}
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else /* For channels 0 to 9 */
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{
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MODIFY_REG(hadc->Instance->SMPR2 ,
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ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel) ,
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ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
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}
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/* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor */
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/* and VREFINT measurement path. */
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if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
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(sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
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{
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SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
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}
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/* Configure the offset: offset enable/disable, InjectedChannel, offset value */
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switch(sConfigInjected->InjectedRank)
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{
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case 1:
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/* Set injected channel 1 offset */
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MODIFY_REG(hadc->Instance->JOFR1,
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ADC_JOFR1_JOFFSET1,
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sConfigInjected->InjectedOffset);
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break;
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case 2:
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/* Set injected channel 2 offset */
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MODIFY_REG(hadc->Instance->JOFR2,
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ADC_JOFR2_JOFFSET2,
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sConfigInjected->InjectedOffset);
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break;
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case 3:
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/* Set injected channel 3 offset */
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MODIFY_REG(hadc->Instance->JOFR3,
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ADC_JOFR3_JOFFSET3,
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sConfigInjected->InjectedOffset);
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break;
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case 4:
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default:
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MODIFY_REG(hadc->Instance->JOFR4,
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ADC_JOFR4_JOFFSET4,
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sConfigInjected->InjectedOffset);
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break;
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}
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/* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */
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/* and VREFINT measurement path. */
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if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
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(sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) )
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{
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/* For STM32F1 devices with several ADC: Only ADC1 can access internal */
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/* measurement channels (VrefInt/TempSensor). If these channels are */
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/* intended to be set on other ADC instances, an error is reported. */
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if (hadc->Instance == ADC1)
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{
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if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET)
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{
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SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
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if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR))
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{
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/* Delay for temperature sensor stabilization time */
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/* Compute number of CPU cycles to wait for */
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wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000U));
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while(wait_loop_index != 0U)
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{
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wait_loop_index--;
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}
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}
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}
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}
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else
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{
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/* Update ADC state machine to error */
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SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
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tmp_hal_status = HAL_ERROR;
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}
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}
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/* Process unlocked */
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__HAL_UNLOCK(hadc);
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/* Return function status */
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return tmp_hal_status;
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}
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#if defined (STM32F103x6) || defined (STM32F103xB) || defined (STM32F105xC) || defined (STM32F107xC) || defined (STM32F103xE) || defined (STM32F103xG)
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/**
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* @brief Enable ADC multimode and configure multimode parameters
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* @note Possibility to update parameters on the fly:
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* This function initializes multimode parameters, following
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* calls to this function can be used to reconfigure some parameters
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* of structure "ADC_MultiModeTypeDef" on the fly, without reseting
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* the ADCs (both ADCs of the common group).
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* The setting of these parameters is conditioned to ADC state.
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* For parameters constraints, see comments of structure
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* "ADC_MultiModeTypeDef".
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* @note To change back configuration from multimode to single mode, ADC must
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* be reset (using function HAL_ADC_Init() ).
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* @param hadc: ADC handle
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* @param multimode: Structure of ADC multimode configuration
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* @retval HAL status
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*/
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HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
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{
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HAL_StatusTypeDef tmp_hal_status = HAL_OK;
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ADC_HandleTypeDef tmphadcSlave;
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/* Check the parameters */
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assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
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assert_param(IS_ADC_MODE(multimode->Mode));
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/* Process locked */
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__HAL_LOCK(hadc);
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/* Set a temporary handle of the ADC slave associated to the ADC master */
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ADC_MULTI_SLAVE(hadc, &tmphadcSlave);
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/* Parameters update conditioned to ADC state: */
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/* Parameters that can be updated when ADC is disabled or enabled without */
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/* conversion on going on regular group: */
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/* - ADC master and ADC slave DMA configuration */
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/* Parameters that can be updated only when ADC is disabled: */
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/* - Multimode mode selection */
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/* To optimize code, all multimode settings can be set when both ADCs of */
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/* the common group are in state: disabled. */
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if ((ADC_IS_ENABLE(hadc) == RESET) &&
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(ADC_IS_ENABLE(&tmphadcSlave) == RESET) &&
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(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)) )
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{
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MODIFY_REG(hadc->Instance->CR1,
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ADC_CR1_DUALMOD ,
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multimode->Mode );
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}
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/* If one of the ADC sharing the same common group is enabled, no update */
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/* could be done on neither of the multimode structure parameters. */
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else
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{
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/* Update ADC state machine to error */
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SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
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tmp_hal_status = HAL_ERROR;
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}
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/* Process unlocked */
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__HAL_UNLOCK(hadc);
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/* Return function status */
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return tmp_hal_status;
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}
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#endif /* defined STM32F103x6 || defined STM32F103xB || defined STM32F105xC || defined STM32F107xC || defined STM32F103xE || defined STM32F103xG */
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* HAL_ADC_MODULE_ENABLED */
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/**
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* @}
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*/
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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