mirror of
https://github.com/Klipper3d/klipper.git
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93 lines
7.7 KiB
C
93 lines
7.7 KiB
C
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/* ---------------------------------------------------------------------------- */
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/* Atmel Microcontroller Software Support */
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/* SAM Software Package License */
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/* ---------------------------------------------------------------------------- */
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/* Copyright (c) %copyright_year%, Atmel Corporation */
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/* */
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/* All rights reserved. */
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/* */
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/* Redistribution and use in source and binary forms, with or without */
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/* modification, are permitted provided that the following condition is met: */
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/* */
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/* - Redistributions of source code must retain the above copyright notice, */
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/* this list of conditions and the disclaimer below. */
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/* */
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/* Atmel's name may not be used to endorse or promote products derived from */
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/* this software without specific prior written permission. */
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/* */
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/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
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/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
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/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
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/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
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/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
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/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
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/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
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/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
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/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
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/* ---------------------------------------------------------------------------- */
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#ifndef _SAM4E_USART1_INSTANCE_
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#define _SAM4E_USART1_INSTANCE_
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/* ========== Register definition for USART1 peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_USART1_CR (0x400A4000U) /**< \brief (USART1) Control Register */
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#define REG_USART1_MR (0x400A4004U) /**< \brief (USART1) Mode Register */
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#define REG_USART1_IER (0x400A4008U) /**< \brief (USART1) Interrupt Enable Register */
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#define REG_USART1_IDR (0x400A400CU) /**< \brief (USART1) Interrupt Disable Register */
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#define REG_USART1_IMR (0x400A4010U) /**< \brief (USART1) Interrupt Mask Register */
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#define REG_USART1_CSR (0x400A4014U) /**< \brief (USART1) Channel Status Register */
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#define REG_USART1_RHR (0x400A4018U) /**< \brief (USART1) Receiver Holding Register */
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#define REG_USART1_THR (0x400A401CU) /**< \brief (USART1) Transmitter Holding Register */
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#define REG_USART1_BRGR (0x400A4020U) /**< \brief (USART1) Baud Rate Generator Register */
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#define REG_USART1_RTOR (0x400A4024U) /**< \brief (USART1) Receiver Time-out Register */
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#define REG_USART1_TTGR (0x400A4028U) /**< \brief (USART1) Transmitter Timeguard Register */
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#define REG_USART1_FIDI (0x400A4040U) /**< \brief (USART1) FI DI Ratio Register */
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#define REG_USART1_NER (0x400A4044U) /**< \brief (USART1) Number of Errors Register */
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#define REG_USART1_IF (0x400A404CU) /**< \brief (USART1) IrDA Filter Register */
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#define REG_USART1_MAN (0x400A4050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
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#define REG_USART1_WPMR (0x400A40E4U) /**< \brief (USART1) Write Protect Mode Register */
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#define REG_USART1_WPSR (0x400A40E8U) /**< \brief (USART1) Write Protect Status Register */
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#define REG_USART1_RPR (0x400A4100U) /**< \brief (USART1) Receive Pointer Register */
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#define REG_USART1_RCR (0x400A4104U) /**< \brief (USART1) Receive Counter Register */
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#define REG_USART1_TPR (0x400A4108U) /**< \brief (USART1) Transmit Pointer Register */
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#define REG_USART1_TCR (0x400A410CU) /**< \brief (USART1) Transmit Counter Register */
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#define REG_USART1_RNPR (0x400A4110U) /**< \brief (USART1) Receive Next Pointer Register */
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#define REG_USART1_RNCR (0x400A4114U) /**< \brief (USART1) Receive Next Counter Register */
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#define REG_USART1_TNPR (0x400A4118U) /**< \brief (USART1) Transmit Next Pointer Register */
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#define REG_USART1_TNCR (0x400A411CU) /**< \brief (USART1) Transmit Next Counter Register */
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#define REG_USART1_PTCR (0x400A4120U) /**< \brief (USART1) Transfer Control Register */
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#define REG_USART1_PTSR (0x400A4124U) /**< \brief (USART1) Transfer Status Register */
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#else
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#define REG_USART1_CR (*(WoReg*)0x400A4000U) /**< \brief (USART1) Control Register */
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#define REG_USART1_MR (*(RwReg*)0x400A4004U) /**< \brief (USART1) Mode Register */
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#define REG_USART1_IER (*(WoReg*)0x400A4008U) /**< \brief (USART1) Interrupt Enable Register */
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#define REG_USART1_IDR (*(WoReg*)0x400A400CU) /**< \brief (USART1) Interrupt Disable Register */
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#define REG_USART1_IMR (*(RoReg*)0x400A4010U) /**< \brief (USART1) Interrupt Mask Register */
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#define REG_USART1_CSR (*(RoReg*)0x400A4014U) /**< \brief (USART1) Channel Status Register */
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#define REG_USART1_RHR (*(RoReg*)0x400A4018U) /**< \brief (USART1) Receiver Holding Register */
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#define REG_USART1_THR (*(WoReg*)0x400A401CU) /**< \brief (USART1) Transmitter Holding Register */
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#define REG_USART1_BRGR (*(RwReg*)0x400A4020U) /**< \brief (USART1) Baud Rate Generator Register */
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#define REG_USART1_RTOR (*(RwReg*)0x400A4024U) /**< \brief (USART1) Receiver Time-out Register */
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#define REG_USART1_TTGR (*(RwReg*)0x400A4028U) /**< \brief (USART1) Transmitter Timeguard Register */
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#define REG_USART1_FIDI (*(RwReg*)0x400A4040U) /**< \brief (USART1) FI DI Ratio Register */
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#define REG_USART1_NER (*(RoReg*)0x400A4044U) /**< \brief (USART1) Number of Errors Register */
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#define REG_USART1_IF (*(RwReg*)0x400A404CU) /**< \brief (USART1) IrDA Filter Register */
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#define REG_USART1_MAN (*(RwReg*)0x400A4050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
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#define REG_USART1_WPMR (*(RwReg*)0x400A40E4U) /**< \brief (USART1) Write Protect Mode Register */
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#define REG_USART1_WPSR (*(RoReg*)0x400A40E8U) /**< \brief (USART1) Write Protect Status Register */
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#define REG_USART1_RPR (*(RwReg*)0x400A4100U) /**< \brief (USART1) Receive Pointer Register */
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#define REG_USART1_RCR (*(RwReg*)0x400A4104U) /**< \brief (USART1) Receive Counter Register */
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#define REG_USART1_TPR (*(RwReg*)0x400A4108U) /**< \brief (USART1) Transmit Pointer Register */
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#define REG_USART1_TCR (*(RwReg*)0x400A410CU) /**< \brief (USART1) Transmit Counter Register */
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#define REG_USART1_RNPR (*(RwReg*)0x400A4110U) /**< \brief (USART1) Receive Next Pointer Register */
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#define REG_USART1_RNCR (*(RwReg*)0x400A4114U) /**< \brief (USART1) Receive Next Counter Register */
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#define REG_USART1_TNPR (*(RwReg*)0x400A4118U) /**< \brief (USART1) Transmit Next Pointer Register */
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#define REG_USART1_TNCR (*(RwReg*)0x400A411CU) /**< \brief (USART1) Transmit Next Counter Register */
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#define REG_USART1_PTCR (*(WoReg*)0x400A4120U) /**< \brief (USART1) Transfer Control Register */
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#define REG_USART1_PTSR (*(RoReg*)0x400A4124U) /**< \brief (USART1) Transfer Status Register */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#endif /* _SAM4E_USART1_INSTANCE_ */
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